1. Field of the Invention
This invention relates to the field of memory arrays and in particular to a circuitry for programming redundant memory.
2. Prior Art
A memory array, such as a random access memory (RAM) or an erasable programmable read-only-memory (EPROM), is generally comprised of binary elements arranged in a matrix of rows and columns. Addresses associated with the array access memory locations within the array. Typically, decoders are coupled to the memory to provide the decoding of the address signal for accessing the various binary elements, which are also referred to as memory cells. The inputs to the array are provided on the word lines, which are usually the row lines, and outputs from the array are provided on the bit lines, which are usually the column lines. The design and manufacture of various semiconductor memories and memory arrays are well-known in the prior art.
In the manufacture of such memory arrays, processing defects often randomly occur across the memory chip. In most instances, these memory chips are fully functional except for a single or a small number of rows or columns containing the defective cells(s). In order not to scrap a chip for having a single or a small number of defects, defect tolerant memory devices have been devised in which a redundant row and/or column of cells is substituted for a selected row and/or column containing the defective cell(s).
Various prior art schemes for providing fault tolerant memory are described in U.S. Pat. Nos. 3,659,275; 3,735,368; 3,753,244; 3,753,235; and 4,051,354. In U.S. Pat. No. 4,250,570, the redundant memory circuit programs the redundant decoders coupled to the redundant rows or columns, having initially unspecified addresses, to match the addresses of defective rows or columns having addresses associated therewith and disables one or more of the defective rows or columns having addresses associated therewith. The programming of the decoder is achieved by the use of fusible links, wherein the address decoding is achieved by open circuiting selected fusible links.
An improved addressing scheme for single chip memories, which includes a plurality of redundant lines and associated cells, is taught in U.S. Pat. Nos. 4,358,833 and 4,441,170. Aside from fusible links, other schemes are known for providing the programming circuitry to program the redundancy circuit. That is, once the defective cells are located, the redundancy circuit must be programmed, so that address signals which would access the defective cells are rerouted to the redundant memory.
Further, another scheme for providing redundant programming is achieved by the use of a content addressable memory (CAM). A CAM provides for storing the addresses of defective locations of the main memory array. One such defect tolerant memory system using a CAM is taught in U.S. Pat. No. 3,633,175. However, more recently semiconductor memory devices utilize redundancy schemes where the redundancy storage elements in the CAMs are similar to the cells used in the main memory. Instead of fusible links, actual memory cells are used to provide the programming. One such example is described in a copending application Ser. No. 309,320, filed Feb. 10, 1989, entitled "Redundancy Decoding Circuit Using N-Channel Transistors".
However, it is to be noted that in the programming of redundant memory, those redundant addresses are provided by a special redundancy programming circuitry which blows the fuses in the fusible link scheme or stores a given state in a CAM cell scheme. These redundant programming circuitry are generally coupled to receive address signals which are then used to provide the programming voltage. Where CAM cells are used, such as EPROM CAM cells, the redundant programming circuit must basically include a duplication of the main memory programming circuit in order to program the redundant EPROM cells.
It is appreciated that by combining a portion of the main memory programming circuitry with the redundancy programming circuitry, some of the duplication can be alleviated.